High rate electric field driven nanoelement assembly on an insulated surface

ABSTRACT

A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. application Ser. No.13/990,388, filed May 29, 2013, which is the U.S. national phaseapplication of PCT/US11/62395, filed Nov. 29, 2011, which claims thepriority of U.S. Provisional Application No. 61/417,658 filed Nov. 29,2010, both of which are hereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

The invention was made with support from Grant EEC-0425826 from theNational Science Foundation Nanoscale Science and Engineering Center.The United States Government has certain rights in the invention.

BACKGROUND

Nanoelements have generated much interest due to their potential use indevices requiring nanoscale features such as new electronic devices,sensors, photonic crystals, advanced batteries, and many otherapplications (1,2). The realization of commercial applications, however,depends on developing high-rate and precise assembly techniques to placethese elements onto desired locations and surfaces.

Different approaches have been used to carry out directed assembly ofnanoelements in a desired pattern on a substrate, each approach havingdifferent advantages and disadvantages. In electrophoretic assembly,charged nanoelements are driven by an electric field onto a patternedconductor. This method is fast, with assembly typically taking less thana minute; however, it is limited to assembly on a conductive substrate(3). Directed assembly can also be carried out onto a chemicallyfunctionalized surface. For example, treatment to render a surface morehydrophilic can lead to selective assembly of nanoelements on thetreated area (4,5). However, such assembly is a slow process, requiringup to several hours, because it is diffusion limited (6-9). Thus, thereremains a need for a method of nanoelement assembly that is both rapidand not reliant on having either a conductive surface or a chemicallyfunctionalized surface.

SUMMARY OF THE INVENTION

The invention provides methods and materials for high rate assembly ofnanoelements into two-dimensional patterns on a substrate for theproduction of microscale and nanoscale circuits and other electronicdevices. The methods utilize the electric field contours emanating froma conductive layer covered by an insulating layer and a patternedphotoresist layer to drive nanoelements from a liquid suspension toselected assembly sites on the insulating layer surface. The continuedapplication of the electric field allows the assembled nanoelements tobe rapidly withdrawn from the suspension in an assembled state.

One aspect of the invention is a method for assembling nanoelements. Themethod includes the steps of: providing a patterned substrate having abase nonconducting layer, a conducting layer on the base layer, aninsulated layer on the conducting layer, and a patterned layer on theinsulating layer; submerging at least a portion of the substrate into aliquid suspension of nanoelements, the suspension interfacing with agaseous medium, such as air, at a surface of the suspension; and pullingthe submerged portion of the substrate through the surface of thesuspension while applying an electrical potential between the conductinglayer and a counter electrode in the suspension. The patterned layercontains one or more voids, whose walls are formed by the patternedlayer and whose bottom is formed by the insulating layer. As a result ofthe method, nanoelements from the suspension are assembled in the voidsand deposited on the insulating layer of the patterned substrate.

Another aspect of the invention is a patterned substrate for use withthe nanoelement assembly method. The patterned substrate includes a baselayer, a conducting layer above the base layer, an insulating layerabove the conducting layer, and a patterned layer above the insulatinglayer. The patterned layer is interrupted according to a pattern thatdefines one or more voids therein. The patterned layer forms the wallsof the voids, and the insulating layer forms the bottom of the voids.The thickness of the insulating layer is selected so as to provideselective assembly of the nanoelements within the voids during thenanoelement assembly method, leaving other surfaces of the patternedsubstrate essentially devoid of nanoelements.

Still another aspect of the invention is a method of making thepatterned substrate. The method includes the steps of: depositing aconductive layer on a base layer of non-conducting material; depositinga nonconductive layer on the conductive layer; depositing a photoresistlayer on the insulating layer; and performing lithography to remove oneor more portions of the photoresist layer to create a pattern of voidsin the photoresist layer, whereby a patterning layer is formed, thepatterning layer comprising a pattern of voids, the walls of the voidsformed by the patterning layer and the bottom of the voids formed by theinsulating layer.

Yet another aspect of the invention is a device for assemblingnanoelements according to the method described above. The deviceincludes a chamber for containing a suspension of nanoelements, acounter electrode disposed within the chamber, and a movable platformadapted for mounting a patterned substrate. The movable platform isattached to a drive capable of pulling the platform through the surfaceof the suspension at a speed adjustable from about 0.5 to about 10mm/min.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagrammatic representation of a method of assemblingnanoelements according to the invention.

FIG. 2 shows a cross section of a patterned substrate for the assemblyof nanoelements.

FIG. 3 shows a diagram of an apparatus for carrying out a nanoelementassembly method according to the invention.

FIGS. 4A and 4B show a scanning electron micrograph (SEM) of an assemblyresult using a pulling speed of 3 mm/min and an applied voltage of 3.4 Vusing polystyrene latex nanoparticles of 48 nm average size. FIG. 4Ashows a low magnification image, and FIG. 4B shows a high magnificationimage. In FIG. 4B the assembled nanoparticles can be discerned.

FIG. 5 shows SEM images for assembly performed at a pulling speed of 5mm/min using the indicated voltages. The patterned substrate containedvertically oriented nanoscale trenches. Light gray regions indicate noassembly, and dark regions indicate assembly of polystyrene latex (PSL)nanoparticles. Inset panels at the 0V and 3V conditions are highmagnification images showing no assembly at 0V and full assembly at 3V.

FIG. 6 shows assembly results visualized as SEM images for 50 nm PSLnanoparticles in nanotrenches having various orientations (vertical,diagonal, horizontal, intersecting) with respect to the surface of thenanoelement suspension.

FIG. 7 shows the magnitude of the electric field as a function of thedistance from the insulated surface for insulating layers of differentthickness.

FIG. 8 shows the magnitude of the electric field as a function of theinsulating layer thickness.

FIG. 9 shows the effect of nanoscale trench geometry of an insulatedpatterned substrate on the modeled electric field contours.

FIG. 10 shows the effect of nanoscale trench geometry on the modeledelectric field contours for a non-insulated, bare gold conductor at thebottom of the trench.

DETAILED DESCRIPTION OF THE INVENTION

Electrophoresis of nanoelements is known to produce rapid assembly ofthe nanoelements onto an electrically conductive surface which serves asan electrode. However, assembly of nanoelements onto a nonconductivesurface is normally limited by the rate of diffusion of the nanoelementsthrough a liquid suspension to the surface, resulting in assembly ratesorders of magnitude slower than electrophoresis. The present inventorshave discovered that application of an electric field unexpectedlyenhances the rate of nanoelement assembly onto a substrate covered withan electrical insulator at the assembly surface as the surface is pulledthrough the surface of a liquid suspension of nanoelements.

While electrophoresis requires the production of a patterned electrode,leaving a bare conductor exposed to the solution and subject tocomplications such as chemical corrosion, contamination, anddelamination, the new method of the present invention can drive therapid and directed (i.e., patterned) assembly of nanoelements withoutthe need to create a patterned electrode. The new method can drive theassembly of nanoelements using a continuous, unpatterned conductivelayer covered by a continuous, unpatterned insulating layer of selectedthickness. Patterning of the assembled nanoelements can be determined bya patterned layer deposited onto the insulating layer. The patternedlayer can be fabricated from a photoresist material and patterned by alithography method in fewer steps than are required to fabricate apatterned conductive electrode. The result of the assembly method of thepresent invention is a rapidly fabricated patterned assembly ofnanoelements deposited onto a nonconductive surface.

The assembly method is summarized in FIG. 1. A patterned nanosubstrateis made by depositing a conductive layer, such as a metal, onto a baselayer, depositing an insulating material onto the conductive layer, andcoating the insulating layer with a photoresist layer. The photoresistlayer is subjected to lithography, whereby a pattern of voids is createdto form a patterned uppermost layer. Assembly is then carried out byplacing the patterned substrate into a liquid suspension of nanoelementsin a container, and lifting the substrate through the surface of thesuspension while applying a voltage between the conductive layer of thesubstrate and a counter electrode in the suspension. As a result,nanoelements are assembled from the suspension to fill the patternedvoids on the substrate.

According to one embodiment of the invention, a patterned substrate isprovided for carrying out the electrophoretic assembly of nanoelementson a non-conductive surface. A diagram of the substrate is shown in FIG.2. Patterned substrate 10 includes base layer 20, conductive layer 30above the base layer, insulating layer 40 above the conducting layer,and patterned layer 50 above the insulating layer. The patterned layeris interrupted according to a pattern that defines one or more voids 60in the patterned layer for the assembly of nanoelements. The patternedlayer material forms the sidewalls of the voids, while the underlyinginsulating layer forms the bottom or floor of the voids. Assembly takesplace on the bottom of the voids and is laterally limited by thepresence of the sidewalls. The thickness of the insulating layer,together with the geometry of the voids, leads to the desired electricfield contours that direct the assembly of nanoelements within the voidsduring electrophoresis. The electric field contour results in selectivenanoelement assembly method in the voids, leaving other surfaces of thepatterned substrate, outside the voids, essentially free or evenentirely devoid of nanoelements.

The patterned substrate can be fabricated by depositing a conductivelayer on a base layer of nonconducting material, then depositing anonconductive layer on the conductive layer, and then depositing aphotoresist layer on the insulating layer. Finally, the photoresistlayer is patterned by performing lithography to remove one or moreportions of the photoresist layer, thereby creating a pattern of voidsin the photoresist layer. In some embodiments, the patterned substrateconsists only or essentially of the base layer, conductive layer,insulating layer, and patterned layer. In other embodiments, additionalmaterials or layers can be added in between, above, or below thoselayers. For example, an optional adhesion layer can be added between thebase layer and the conductive layer to improve adhesion of theconductive layer and reduce the tendency for delamination duringelectrophoresis. With respect to the insulating and patterned layer, insome embodiments they are separate and distinct layers, made ofdifferent materials and in different steps of the method of fabrication.In other embodiments, the insulating and patterned layers are combinedinto a single structure, which has a lower portion that covers theconductive layer and forms the bottom or floor of the voids, and anupper portion that is interrupted by the pattern that forms the voids.Such a combined patterned insulating layer can be formed, for example,by an imprinting method (e.g., nanoimprinting), in which a single layerof insulating material is formed followed by removal of a portion of theupper portion thereof to form a pattern of voids (patterned layer)underlayered by a continuous insulating layer.

The base layer can be any supportive and non-conductive materialsuitable for depositing a conductive layer thereon. It providesmechanical support for the rest of the materials in the patternedsubstrate and also insulates the conductive layer on the side oppositefrom assembly. The base layer can be rigid or it can be flexible.Suitable materials include silicon, silicon dioxide, a metal oxide suchas alumina or titania, sapphire, silicon carbide, other inorganic orceramic materials, semiconductor materials, and non-conductive organicpolymers. The base layer can be formed by known methods, includingmolding, polymerization, cutting from a block or ingot, polishing, andvarious physical and chemical deposition methods. The dimensions of thebase layer can be determined by the particular application. In general,the base layer is thicker than the other layers of the patternedsubstrate, and may be thicker than all the other layers combined. Mostapplications will require that the base layer, and the overall patternedsubstrate, have an approximately planar shape and a surface area of atleast 1, 10, 100, or 1000 or more μm². The thickness of the base layercan be at least 100 nm, 500 nm, 1 μm, 10 μm or more. The base layer ofthe patterned substrate can also be a portion of a larger device thatcan have any desired shape or dimensions.

The conductive layer is a thin layer of a conductive metal, metal alloy,or a conductive polymer. The conductive layer covers all or a portion ofthe base layer and can be patterned or unpatterned. In some embodiments,the conductive layer covers the entire base layer and is unpatterned.Suitable metals include gold, silver, copper, chromium, aluminum,titanium, tungsten, and platinum, as well as alloys thereof. In someembodiments, the conductive layer comprises or consists of gold. In someembodiments, the conductive layer, such as gold, is deposited onto anadhesion layer of chromium. Standard processes can be used to depositone or more metal or polymer layers on the base layer or an adhesionlayer to form the conductive layer. These layers can be deposited by anymethod that provides a generally homogeneous, thin layer with goodmolecular contact and adhesion to adjacent layers. For example, chemicalvapor deposition and physical vapor deposition are suitable methods fordepositing metals. A preferred method for depositing metals issputtering. Conductive polymers can be deposited by polymerization or byelectrophoresis (see U.S. Published Patent Application 2009-0134033A1,which is incorporated herein by reference). Suitable conductive polymersinclude poly(styrenesulfonate)-poly(2,3-dihydrothieno(3,4-1,4-dioxin),polyacetylene, polydiacetylene, polypyrrole, polyanaline, polythiophene,poly(p-phenylene), polyazulene and polyquinoline. The conductive layeris a thin layer and can have a thickness, for example, in the range fromabout 40 nm to about 100 nm.

The insulating layer is a layer of non-conductive material depositedabove or directly on the conductive layer. The material of theinsulating layer can be, for example, silicon dioxide, any dielectricmaterial, or a non-conductive polymer. A suitable dielectric material isan electrically insulating solid material that can become polarized inan electric field, such as a glass, a ceramic, or a plastic. Thedielectric material of the insulating layer can be, for example, a thinlayer of silicon dioxide deposited by plasma enhanced chemical vapordeposition (PECVD), or another chemical or physical depositiontechnique. The thickness of the insulating layer can be in the rangefrom about 50 nm to about 5 μm, or about 50 nm to about 1 μm, such as atleast 50 nm, at least 100 nm, at least 150 nm, at least 300 nm, at least500 nm, or at least 1 μm. The assembly parameters will vary as afunction of the dielectric thickness because the electric fieldgenerated at the voids depends on the thickness of the insulating layer,as well as other factors. See below for further discussion. The lateralextent of the insulating layer is typically sufficient to cover theentire conductive layer. In this way, the electric field will be uniformacross the patterned substrate, and will be modified solely by thepatterned layer as desired for the assembly of nanoelements.

The patterned layer can be formed of any desired electrically insulatingmaterial. A convenient material is a photoresist material such aspoly(methylmethacrylate) (PMMA), which is electrically insulating andcan be patterned using a lithographic method. Lithographic methods arewell known, and can be selected based on the size of the patternfeatures. For example, pattern features in the nm range can be createdusing electron beam lithography. Larger scale features, in the micronrange, can be created using photolithography. If it is desired totransfer the assembled nanoelements from the patterned substrate wherethey are created to another substrate, then the patterned layer shouldbe fabricated from a material that can be readily removed withoutdisrupting the assembled nanoelements or the underlying layers. Forexample, PMMA can be dissolved using acetone, leaving the assemblednanoelements resting on a silicon dioxide insulating layer, ready fortransfer to another substrate, where they can be integrated into acircuit or sensor. The thickness of the patterned layer is less crucialthan that of the insulating layer in terms of its effect on the electricfield strength. As the simulations presented below demonstrate, thefield is highest within the voids, near the insulating layer. However,the patterned layer also serves to laterally concentrate the fieldwithin the voids, and also contributes to the driving force forassembly. Therefore, the patterned layer can be deposited initially at athickness in a similar range as the thickness of the insulating layer,i.e., about 50 nm to about 5 μm or more. Following lithography, thethickness of the patterned layer will be reduced to essentially zerowithin the voids, and between the voids may remain at its originalthickness. The thickness of the patterned layer generally will becomethe depth of the voids. The patterned layer can be deposited by knownmethods, such as methods for depositing photoresist materials. Apreferred method is spin coating.

In certain embodiments the patterned layer and the insulating layer canbe merged into a single layer. For example, a photoresist material canalso serve as an electrically insulating material for the insulatinglayer. In such embodiments, the assembly pattern can be created in thecombined insulating patterned layer using an imprinting method, such asnanoimprinting (10), which removes material from the combined layer to adesired depth to form the voids, leaving sufficient insulating materialto cover the conductive layer and provide the appropriate electric fieldfor assembly.

The patterned layer contains one or more voids, or empty spaces in thepatterned layer, which are intended as the locations for nanoelementassembly. The voids can form a two-dimensional pattern that serves asthe basis for a circuit, a portion of a circuit, or as a sensor, orother component of a nanoscale or microscale electronic orelectromechanical device. The assembly method is capable of achievingassembly of nanoelements in voids that define any desiredtwo-dimensional pattern, including any desired geometric shapes, ornetworks of trenches or lines that run vertically, horizontally, ordiagonally, or that intersect with other trenches, lines, or geometricfigures. The lateral dimensions of the voids, and of the resultingassembled nanoelement features, can be any desired size in the nanoscale(from about 1 to about 999 nm) or microscale (from about 1 to about 999μm) range, or even larger. The depth of the voids is determined by thethickness of the patterned layer.

Many different types of nanoelements can be assembled using the methodof the present invention. These include nanoparticles, nanorods,nanotubes, nanocrystals, dendrimers, nanowires; biological materials,including protein molecules (native or recombinant), antibodies, nucleicacid molecules, polysaccharide molecules, lipids, complexes of suchmolecules and mixtures of such molecules; cells, lipid vesicles, andnative or recombinant virus particles; quantum dots; and organicnanotubes. Preferred nanoelements are single-walled carbon nanotubes andnanoparticles. Nanoelements having an elongated shape can be assembledwithin nanotrenches in an aligned or partially aligned fashion bylimiting the width of the trenches. The alignment is produced by stericinteraction during the assembly process. See U.S. Published PatentApplication 2010-0183844A1, which is hereby incorporated by reference.Nanoelements for use in the invention must be charged and possess asufficient surface potential (zeta potential) under the conditions ofassembly in order to be responsive to the applied electric field. Thecharge and surface potential can be manipulated for most nanoelements bycontrolling the pH of an aqueous nanoparticle suspension, the ionicenvironment (e.g., ionic strength) of the nanoparticles in suspension,and the solvent used for the nanoparticle suspension (solvent polarity).These influences are well known and can be adjusted as needed tooptimize the assembly process.

The patterned substrate is contemplated for use in a nanoelementassembly method that relies on electrophoresis to counteract shearforces at the air-water interface of a solution which tend to disruptthe assembled structures. In the absence of an electric field, removalof a substrate containing assembled nanoelements through the surface ofa liquid suspension is believed to promote the removal of the assemblednanoelements from the substrate. Without intending to limit theinvention to any particular mechanism, it is believed that in thepresent assembly method the nanoelements are rapidly (within seconds)assembled on the submerged patterned substrate in the presence of theapplied electric field, and that the field must be continuously appliedduring removal of the substrate through the suspension surface, i.e.,through a liquid-gas interface, in order to prevent shear forces fromdisrupting and removing the assembled nanoelements. In order to preventsuch disruption, a previous method required the substrate to bechemically treated to promote the adhesion of the nanoelements andwithdrawn very slowly (e.g., 0.1 mm/min) from the suspension. See U.S.Published Patent Application 2010-0183844A1. The present inventiondramatically speeds up the withdrawal process and maintains theassembled nanoelement structures through the use of an electric fieldthat is applied prior to and during removal of the substrate.

The patterned substrate is also contemplated for use in devices whichrequire nanoelements to be assembled on a non-conductive surfacematerial. This is a requirement for certain applications, such asquantum dot memory, single walled nanotube transistors, and singleelectron devices. The substrate can also be used to prepare biosensorsthat lack any exposed metal. For example, the methods and devicesdescribed in U.S. Published Patent Application 2011-0117582A1 (herebyincorporated by reference) can be combined with the subject matter ofthe present invention to fabricate biosensors based on assemblednanoelements, e.g., by attaching antibodies or other biomolecules tonanoparticles.

Yet another application of the patterned substrate is as a component ofa nanoelement printing system. In this application, the assemblednanoelements are transferred from the assembly substrate onto a receptorsubstrate. To make this possible, the affinity of the assemblednanoelements for the assembly substrate should be sufficient to maintainthe assembled structure, but not so strong as to resist transfer to thereceptor substrate. Here, the use of an insulating layer as the assemblysurface is important, as it provides an appropriate nanoelement affinityfor the subsequent transfer of the assembly.

A voltage is applied between the conductive layer of the patternedsubstrate and a counter electrode placed in the nanoelement suspension.The appropriate voltage can be determined by considering severaladditional factors that affect the rate of assembly. Those factorsinclude the distance between the electrodes, the nanoparticleconcentration, the zeta potential of the nanoparticles, the pH of thenanoparticle suspension, the nature of the solvent and the conductivityof the nanoparticle suspension, the pattern geometry of the voids whereassembly takes place, and the speed with which the substrate is pulledacross the surface of the nanoelement suspension.

The distance between the counter electrode and the patterned substrate(which functions at the other electrode) determines the strength of theelectric field that exerts a force on the particles, causing them tomigrate towards the patterned substrate. The distance between theelectrodes is preferably between about 2 mm and about 5 mm, though agreater or lesser distance also can be used with suitable adjustments tothe applied voltage to maintain an equivalent field strength.

In some embodiments of the assembly method the electrical potentialapplied is a DC potential between about 1V and about 5V, or betweenabout 2V and 4V though higher or lower values can be used. Whennon-polar solvents are used in the nanoparticle suspension, much highervoltages, up to 200V, may be required to establish an electric fieldsufficient to drive nanoelement assembly. The potential can be constantor can vary with time during nanoelement deposition. Rapidly varyingpotentials, such as obtained using an AC voltage source, will tend tonegate the insulating effect of the insulating layer and candramatically alter the contour and strength of the electric field.Therefore, DC voltage is preferred. Certain fill patterns such as longhorizontally oriented nanotrenches generally may deplete the pool ofnanoelements at the surface of the suspension more rapidly thanvertically oriented features or small, isolated features. Therefore, thespeed of pulling as well as the voltage can be varied over time duringassembly across a given substrate, or for one substrate compared withanother, depending on the amount of horizontal pattern.

The pH of the suspension can be adjusted to an appropriate value becausethe pH affects the net charge and zeta potential of the nanoelements.The pH of the nanoparticle suspension can be adjusted using agents suchas acids, bases, or buffering agents. For the experiments described inthe Examples below, the pH was determined to be in the range from 10.6to 11.2 (e.g., 10.6, 10.7, 10.8, 10.9, 11.0, 11.1, or 11.2). Thecorresponding zeta potential values over this pH range were −45 to −60mV as measured with a Malvern Instruments Zetasizer Nano ZS90. Thecorresponding suspension conductivity values were 39.8 μS to 307 μS, asa result of adding ammonium hydroxide to adjust the pH.

The concentration of the particle suspension has an important effect onthe assembly rate, which is highly dependent on the particleconcentration. A higher nanoelement concentration will produce a higherrate of migration, both electrophoretic and by diffusion or convection,than a lower concentration. The preferred range for particleconcentration is from about 0.005 wt % (˜10¹¹ particles/ml) to about 1wt % (˜10¹⁴ particles/ml). Higher concentration ranges, such as fromabout 0.1 to about 10 wt % also can be used. Since assembly can bemaintained using very slow removal from the solution, even without anapplied voltage under certain conditions, the pulling speed of thepatterned substrate through the suspension surface according to theinvention (i.e., with applied voltage) can have a wide range from about0.05 mm/min to about 5 mm/min, such as at least 1 mm/min, at least 3mm/min, or at least 5 mm/min).

For methods of diffusion-controlled assembly, i.e., without theapplication of an electric field, chemical or physical surfacetreatments may be used in order to establish a pattern of assembly. Forexample, in U.S. Published Patent Application 2010-0183844A1 it wasshown that treating the surface of a substrate to render it morehydrophilic could promote nanoelement assembly in the treated areas,while no assembly takes place in untreated areas. However, with thepresent method, highly specific patterned assembly is achieved accordingto the pattern established by the patterned layer. The patterned layermodifies the contours of the electric field according to its pattern,and therefore produces patterned assembly without the need for chemicalor physical surface modification. Thus, in typical embodiments, theexposed surface of the insulating layer in the voids, where assemblytakes place, is not modified, and has the same relative hydrophilicityor hydrophobicity as the surface of the patterned layer, where assemblydoes not take place. Nevertheless, the two methods can be combined, sothat in other embodiments of the present invention the hydrophilicity orhydrophobicity, or other chemical or physical surface properties, can bemodified so as to utilize two or more different driving forces fornanoelement assembly in a single operation.

FIG. 3 depicts a device for assembling nanoelements using a method ofthe present invention. Nanoelement assembly device 100 includescontainer 110 to accommodate suspension of nanoelements 120, counterelectrode 130 disposed within the container, and movable platform 140adapted for mounting patterned substrate 10, the movable platformattached to drive 150 capable of pulling the platform through a surfaceof the suspension at a speed adjustable from about 0.5 or less to about10 mm/min or more. In some embodiments, the device also includes voltagesource 160, and in some embodiments the device also includes controller170 that can be used to set the voltage and/or the pulling speedaccording to user preferences which are input to the controller orprovided by software that drives the controller. The device can beconfigured with electrical leads that connect the electrodes with thevoltage source. The voltage source should be capable of delivering aconstant DC voltage in the range from about 1V to at least about 200V.In some embodiments, the voltage source is capable of executing aprogrammed series of voltage changes over time. In some embodiments, thedrive for pulling the substrate out of the suspension is programmableand is capable of executing a sequence of different pull speeds overtime. The movable platform has a means for attaching the substrate, suchas a clamp or clasp arrangement.

EXAMPLES Example 1 Nanoparticle Assembly

A patterned substrate was prepared having vertically orientednanotrenches. The trenches were 300 nm wide, 50 μm long, and 150 nmdeep. The substrate was submerged into a suspension having wt % of 48 nmpolystyrene latex nanoparticles (Thermoscientific) at a pH of 10.9. Thecounter electrode was placed at 5 mm from the substrate, and a voltageof 3.4V (positive at the substrate, negative at the counter electrode)as the substrate was pulled through the suspension surface at 3 mm/minusing a KSV NIMA Dip Coater Single Vessel System. The assembly result ispresented in FIGS. 4A and 4B, showing low and high magnification SEMimages. The assembly (dark areas) covered nearly the entire substrate.The high magnification inset shows that the assembled nanoparticlescompletely filled the trenches and that assembly was limited to thetrenches.

Example 2 Effect of Applied Voltage on Nanoparticle Assembly

Nanoparticle assembly was carried out under the conditions of Example 1,but using a pull rate of 5 mm/min and varying the applied voltage asshown in the SEM images of FIG. 5. There was no assembly at 0V and 2V.Assembly started at 2.3V, increasing with voltage. Nearly completeassembly was obtained at 2.7V, and assembly was essentially 100%complete at 3V.

Example 3 Nanoparticle Assembly into Different Two Dimensional VoidPatterns

Polystyrene latex nanoparticles (48 nm) were assembled in different voidpatterns, including nanotrenches (300 nm wide, 5 μm long, 150 nm deep)having vertical, horizontal, diagonal, and intersecting orientations, asshown in the SEM images of FIG. 6. The results confirmed that assemblycan be completed with complete selectivity for the pattern voids in anytwo-dimensional pattern. For the experiments depicted in FIG. 6, thepull rate was 1-3 mm/min, the voltage was 2.9-3.1V, the nanoparticleconcentration was 1 wt %, the pH was 10.9-11.1, and the counterelectrode was 5 mm removed from the substrate.

Example 4 Electric Field Simulations

The electric field was simulated in order to investigate the effect ofinsulating layer thickness, distance from the insulating layer surface,and nanotrench morphology on the contours of the electric field appliedduring nanoelement assembly. The results are shown in FIGS. 7-10.

The commercial computational flow dynamics software FLOW-3D was used tosimulate the electric field near the patterned substrate structure. Thegeometry was modeled as its actual size (no scaling). The electricalproperties of the substrate and other component properties were input tothe system according to references found from literature. The dielectricconstant of the PMMA patterned layer was taken as 2.8, while that of thePECVD oxide insulating layer was taken as 3.9. The conductivity of thesolution was assumed to be 100 μS. A mesh size of 300 nm was usedgenerally, while for the sections that needed more accuracy, such as inthe proximity of patterned structures, fixed points were used todecrease the mesh size at those locations. Boundary conditions weredetermined by first simulating the total area of one pattern (including30-40 trenches) to find out how the electric potential changes betweenthe electrodes. For an applied voltage of 2 to 4 V the electricpotential at 30 μm from the insulating material was found to be 1.2 to2.5 V, and these values were used as a boundary condition to simulatethe exact electric field for one structure, such as a 300 nm wide×150 nmdeep trench.

In FIG. 7 it can be seen that the field strength decreases as thethickness of the insulating layer increases from 100 nm to 1 μm. FIG. 8shows how the field strength attenuates with distance from the surfaceof the insulating layer.

FIG. 9 shows the electric field contours for a trench with an insulatinglayer of 150 nm thickness. FIG. 10 shows electric field contours for atrench with an exposed gold conductive layer (no insulating layer).Without the insulating layer, the electric field strength extendsoutward to the corners at the outer surface of the trench. However, withthe insulating layer in place, the electric field is greatest at thebottom of the trench, especially at the corners.

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That which is claimed is:
 1. A patterned nanosubstrate, thenanosubstrate comprising a base layer of insulating material, a metalconductive layer deposited onto the base layer, an insulating layerdeposited onto the conductive layer, and a patterned layer depositedonto the insulating layer, wherein the patterned layer is interruptedaccording to a pattern that defines one or more voids in the patternedlayer, wherein the patterned layer forms walls of the voids and theinsulating layer forms a bottom of the voids.
 2. The patternednanosubstrate of claim 1, wherein the voids form nanoscale trenches orwells.
 3. The patterned nanosubstrate of claim 1, wherein the base layercomprises a material selected from the group consisting of silicon,silicon dioxide, a semiconductor material, and a non-conductive organicpolymer.
 4. The patterned nanosubstrate of claim 1, wherein theconductive layer comprises a material selected from the group consistingof gold, silver, copper, chromium, aluminum, titanium, platinum, and aconductive polymer.
 5. The patterned nanosubstrate of claim 1, whereinthe insulating layer comprises silicon dioxide, a dielectric material,or a non-conductive polymer.
 6. The patterned nanosubstrate of claim 1,wherein the insulating layer has a thickness in the range from about 50nm to about 5000 nm.
 7. The patterned nanosubstrate of claim 6, whereinthe insulating layer has a thickness of about 150 nm.
 8. The patternednanosubstrate of claim 1, wherein the patterned layer comprises a resistmaterial patterned by a lithographic method.
 9. The patternednanosubstrate of claim 1, wherein the base layer is silicon, theconductive layer is gold, the insulating layer is silicon dioxide, andthe patterned layer is poly(methylmethacryate).
 10. The patternednanosubstrate of claim 1, wherein the voids form a two-dimensionalpattern in the patterning layer.
 11. The patterned nanosubstrate ofclaim 1, wherein the voids comprise two or more nanotrenches thatintersect at one or more junctions.
 12. The patterned nanosubstrate ofclaim 1, wherein the insulating layer and the patterned layer are madeof the same material.
 13. The patterned nanosubstrate of claim 1,wherein the insulating layer and the patterned layer are made ofdifferent materials.
 14. The patterned nanosubstrate of claim 1, whereinthe insulating layer covers the entire conductive layer.
 15. Thepatterned substrate of claim 1, wherein the conductive layer covers theentire base layer.
 16. The patterned nanosubstrate of claim 15, whereinthe insulating layer covers the entire conductive layer.
 17. Thepatterned nanosubstrate of claim 1, further comprising a plurality ofassembled nanoelements contained within one or more of the voids. 18.The patterned nanosubstrate of claim 17, wherein the nanoelements areselected from the group consisting of nanoparticles, nanowires,nanorods, and nanotubes.
 19. The patterned nanosubstrate of claim 18,wherein the nanoelements are nanotubes, nanorods, or nanowires, or amixture thereof; wherein the voids are nanotrenches; and wherein theassembled nanoelements are aligned along a length of the nanotrenches.20. The patterned nanosubstrate of claim 17, wherein the assemblednanoelements form a microscale or nanoscale circuit or sensor or aportion thereof.